Design and performance of "1.25-µm" CMOS for digital applications

This paper presents a detailed approach for the design and performance analysis of 1.25-µm CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-µm CMOS technology, based, in part, on a set of achievable lithographic feature sizes and alignment tolerances together with a set of reasonable process geometric parameters. The process baseline is TWIN-WELL CMOS using n^-epi on an n⁺substrate as the host starting material. Two of the key geometric parameters defined are effective channel length, Le= 1 µm, and gate oxide thickness, tox= 250 Å. Other dimensions have been selected using quasi-scaling rules consistent with a 2λ of 1.25 µm. The design process starts with the selection of the average "well" doping levels from a consideration of some key short-channel effects: simple charge sharing and drain-induced barrier lowering (DIBL). The selection of a suitable operating voltage, VDD, is considered during this process as it effects junction breakdown voltage, gate oxide fields, and more importantly, potential hot-electron injection. Additional process design analyses are presented with respect to the establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed for a basic inverter structure which yields results close to those obtained through more detailed SPICE simulations. A unit delay (single fan-out) analysis is performed yielding delays of 214 ps for a VDDof 5 V and 270 ps for a VDDof 3.3 V.