A BiCMOS dynamic carry lookahead adder circuit for VLSIimplementation of high-speed arithmetic unit |
| |
| Authors: | Kuo J.B. Liao H.J. Chen H.P. |
| |
| Affiliation: | Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; |
| |
| Abstract: | A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder |
| |
| Keywords: | |
|
|
