Back-gate bias effect on the subthreshold behavior and theswitching performance in an ultrathin SOI CMOS inverter operating at 77and 300 K |
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Authors: | Kuo JB Lee WC Sim J-H |
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Affiliation: | Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; |
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Abstract: | The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for VB=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at VB=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field |
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