一种优化可配置的AES密码算法硬件实现

AES加密算法是下一代的常规加密算法，其将被广泛应用在政府部门和商业领域。本文首先介绍了AES加密算法．然后分析了其硬件实现的要点和难点，最后在Xilinx的FPGA VirtexII XC2V3000-4上对AES密码算法进行了实现和验证。本方案采用一种优化的非流水线加密解密数据路径；同时提出了一种新的可配置的动态密钥调度结构，使得该设计支持128、192和256比特的密钥；而且该设计可以配置AES的四种工作模式。实验的结果表明该设计比其它的设计具有更高的性能。

Optimized and Configurable Hardware Implementation of AES Algorithm

The Advanced Encryption Standard (AES) is new symmetric block encryption standard,it is widely applied to government section and commerce organization. Firstly,AES algorithm is introduced in this paper. Then the key features and challenges of AES algorithm implementation of hardware are analyzed. Finally, the circuit of AES algorithm is implemented on Xilinx VirtexII XC2V3000-4 device. A optimized structure of non-pipelined data path of AES is described in this paper. We offer a new and configurable structure of on-flying-key scheduler with 128?192 and 256 bit cipher key. Furthermore, our design can configure four modes of AES operation. Results obtained show that this design has better performance than other FPGA implementation of AES.