| 基于FPGA的SRAM测试电路的设计与实现 |
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| 引用本文： | 田勇,孙晓凌,申华.基于FPGA的SRAM测试电路的设计与实现[J].电子工程师,2008,34(12):57-59. |
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| 作者姓名： | 田勇 孙晓凌 申华 |
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| 作者单位： | 东北大学东软信息学院嵌入式系统工程系,辽宁省大连市,116023 |
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| 基金项目： | 大连市集成电路设计专项研发资金
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| 摘 要： | 为了保证独立的SRAM模块或嵌入式SRAM模块功能的完整性与可靠性，必须对SRAM模块进行测试。介绍了一种基于Ahera DE2开发板的面向字节的SRAM测试电路的设计与实现。测试算法采用分为字内和字间测试两部分的高故障覆盖率March C-算法；设计的测试电路可由标准的JTAG（联合测试工作组）接口进行控制。设计的测试电路可测试独立的SRAM模块或作为BIST（内建自测试）电路测试嵌入式SRAM模块。验证结果表明该SRAM测试系统是非常高效的。
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| 关 键 词： | SRAM(静态随机存储器) MARCH C-算法 JTAG BIST |
Design and Implementation of SRAM Testing Circuit Based on FPGA |
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| TIAN Yong,SUN Xiaoling,SHEN Hua.Design and Implementation of SRAM Testing Circuit Based on FPGA[J].Electronic Engineer,2008,34(12):57-59. |
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| Authors: | TIAN Yong SUN Xiaoling SHEN Hua |
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| Affiliation: | ( Department of Embedded System Engineering, Neusoft Institute of Information, Northeastern University, Dalian 116023, China) |
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| Abstract: | SRAM （Static Random Access Memory ） must be tested for ensuring the functional integrality and reliability of individual or embedded SRAM . This paper presents the design and implementation of word - oriented SRAM testing circuit based on an Altera DE2 development board. The testing algorithm is a word-oriented March C- testing algorithm, covering both bit and word-orientated memory faults. The testing circuit, controlled by a standard JTAG interface, was validated on an Ahera DE2 development board. The results show that the circuitry can test individual or embedded SRAMs in short time and with high fault range. |
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| Keywords: | JTAG BIST |
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