Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

The paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As subchannel DG-HEMT with optimised device structure of 2 nm In_0.48Al_0.52As barrier layer show a peak g_m of 3.09 mS/µm, V_T of 0.29 V, I_ON/I_OFF ratio of 2.24 × 10⁵, subthreshold slope ~73 mV/decade and drain induced barrier lowering ~68 mV/V with f_T and f_max of 776 and 905 GHz at V_ds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.