一种CDC信号滑动窗口时序分析方法

异步时钟域设计中CDC信号的时序分析及收敛是超大规模高频数字电路设计功能正确的重要保证。为了减少设计面积,提出了一种CDC信号滑动窗口时序分析方法,该方法在每种corner的每条CDC通路上单独设置适当的时序约束窗口进行时序计算与分析,有效避免了常用的固定约束分析方法由于约束条件过严导致的虚假时序违反及不必要的时序修复,而使设计面积增大的问题,减轻了CDC电路的后端设计工作量。在16 nm工艺下的实验结果表明,该方法在时钟树偏差较大时与固定约束分析方法相比显著节省了设计面积。

A sliding window timing analysis method of CDC signals

Timing analysis and closure of CDC signals in asynchronous clock domains is an important guarantee to the function correctness of high frequency large scale digital circuits. In order to reduce the design area, a sliding window timing analysis method of CDC signals is proposed, which can execute timing analysis and closure by setting appropriate timing constraint window for each CDC path under each corner. This method can avoid the increase of cell area caused by fake timing violations and unnecessary timing fixing under over-constraint, which often happened in the fixed constraint method. The proposed method can also reduce the backend workload of CDC circuits. The experiment under 16 nm process shows that the proposed method can significantly save the design area compared with the fixed constraint method.