Buffering for vector performance on a pipelined MIMD machine

A technique is presented for obtaining vector performance from a pipelined MIMD computer that does not have hardwired vector instructions. The specific computer in mind is the Denelcor HEP, but the technique might influence the use and possibly even the design of future machines with this type of architecture. This preliminary report presents the basic idea and demonstrates that it can be implemented. Buffering blocks of data to registers is used in conjunction with pipelined floating-point operations to achieve vector performance. Empirical evidence is presented to show that up to 5.8 megaflop performance is possible from the Denelcor HEP on very regular tasks such as matrix vector products. While this rate is not in the ‘super-computer’ range, it is certainly respectable given the hardware capabilities of the HEP (this machine is rated at 10 MIPS peak). This performance indicates that an apparently minor refinement to the architectural design could provide very efficient vector operations in addition to the parallelism and low-overhead synchronization already offered by the HEP architecture.