Defect reduction in Cu dual damascene process using short-loop test structures

This paper outlines the defect reduction measures performed during the development of a 130-nm Cu dual-damascene process. The test methodology, using short-loop test structures, included defect tracing, overlaying defect data and electrical measurement data, physical analyses based on these results, and analyses of defect size distribution. While the defect size distributions for large-scale integration processes are considered to depend on x/sup -k/, the distribution for the Cu dual-damascene process is found to be different and is instead characterized by a cumulative distribution described by the composition of several Lorentzian functions. Using these procedures, defect densities were successfully reduced by 50% in half the time taken previously and without the need for actual products.