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Low-power CMOS threshold-logic gate |
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| Authors: | Avedillo M.J. Quintana J.M. Rueda A. Jimenez E. |
| Affiliation: | Dept. de Diseno Analogico, Seville Univ.; |
| Abstract: | A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design |
| Keywords: | |