7 Gbit/s optical JK flip flop design with two optical AND gates and NOR gates

This study presents a simple methodology for implementation of all optical JK flip flop for future optical high speed networks. The scheme utilizes electronic model of JK flip flop for implementation of all optical JK flip flop at the bit rate of 7 Gbit/s. Firstly, all-optical AND and NOR gates are implemented. Furthermore, with the combination of these basic gate structures, the optical model of JK flip flop is verified. This structure makes use of two optical AND gates and two optical NOR gates. This technique uses a semiconductor optical amplifier (SOA) as the nonlinear medium to produce considerable amount of cross gain and cross phase modulation to attain truth table conditions of optical JK flip flop. In this method, the number of gates is reduced as compared to earlier schemes. Rise time and fall time of 5.6 ps with contrast ratio more than 60 dB are achieved in this design.