一种Virtex系列FPGA配置数据无损压缩算法

随着FPGA规模大幅度提高，配置数据的规模也迅速增加，从而导致FPGA重构时间的增加，并使得存储多个配置的存储器成为基于FPGA的嵌入式系统成本的最大因素.针对Virtex系列FPGA配置数据的结构特点，提出了一种基于LZW改进的配置数据压缩算法，并通过数字信号处理领域和数字通信领域的5个常用模块进行验证，取得了显著的压缩效果.

Lossless Configuration Bitstream Compression for Virtex FPGAs

With the drastical improvements of FPGA's density and performance, the size of the configuration bitstreams has also increased considerably. Therefore, configuration time of FPGA is increasingly becoming a concern, and the memory required for storing various FPGA configuration bitstreams will significantly affect the cost of FPGA-based embedded systems. In this paper, an adaptive LZW algorithm is proposed for compressing the Virtex FPGAs' configuration bitstreams based on detailed analysis of their data regularities. The required decompression hardware is simple. Using this technique, it is demonstrated up to 45.63% compression rate for configuration bitstreams of several real-world applications.