A technique for Improving dual-output domino logic |
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Authors: | Ramprasad S Hajj IN Najm FN |
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Affiliation: | Univ. of Illinois, Urbana, IL, USA; |
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Abstract: | We present a technique, termed clock-generating (CG) domino, for improving dual-output domino logic that reduces area, clock load and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24%, respectively, over dual-output domino and a 48% power reduction for the largest circuit. |
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