语义分割网络的 FPGA 加速计算方法综述

随着深度学习技术的发展和图像场景理解需求的提升,基于现场可编程门阵列(field programmable gate array, FPGA)部署语义分割网络,为用户提供低延迟、高能效的边缘端智能服务成为研究热点。针对语义分割网络结构中计算和存储密集型特点,构建基于FPGA的定制计算结构是研究的重点问题。鉴于此,本文在归纳总结语义分割网络基本原理和计算结构特点的基础上,分别从面向硬件资源约束的模型压缩方法和定制硬件架构设计两个角度阐述基于FPGA的语义分割网络加速计算方法,并重点对硬件架构设计中的计算结构设计和内存访问优化的典型方法进行总结。最后,展望了语义分割网络FPGA加速计算方法的发展趋势,以期为语义分割、边缘计算、定制高能效计算以及其他相关领域的研究者提供设计参考。

A review of FPGA-accelerated computing methods for semantic segmentation network

With the development of deep learning technology and the increasing demand for image scene understanding, the application of semantic segmentation networks based on FPGA to provide low-latency and high-energy-efficiency edge-end intelligent services for all users has become a research hotspot. The computing and storage of the semantic segmentation network structure have the intensive feature. To address this issue, the construction of a customized FPGA-based computing structure is a key research issue. In view of this, this paper summarizes the basic principles of semantic segmentation networks and analyzes the characteristics of its internal calculation structure, then elaborates FPGA-based semantic segmentation network computing acceleration methods from two perspectives: model compression methods with hardware resource constraints and custom hardware architecture design. Furthermore, this paper focuses on a summary and analysis of typical methods of computing structure design and memory access optimization in hardware architecture design. Finally, this paper looks forward to the future development trend of FPGA-accelerated computing methods for semantic segmentation networks, in order to provide design references for researchers in semantic segmentation, edge computing, customized energy-efficient computing and other related fields.