| 低相噪频率合成器的设计与仿真 |
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| 引用本文： | 贾海鹏,张向文.低相噪频率合成器的设计与仿真[J].桂林电子科技大学学报,2012(4):289-292. |
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| 作者姓名： | 贾海鹏 张向文 |
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| 作者单位： | 桂林电子科技大学计算机科学与工程学院 |
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| 基金项目： | 国家自然科学基金(60804059) |
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| 摘 要： | 为了获得低相位噪声和高集成度频率源,设计了基于锁相环的频率合成器。利用ADS射频仿真软件,对锁定时间和相位噪声进行仿真,确定设计满足指标要求。用集成VCO的锁相环芯片ADF4360-7进行硬件测试,锁定频率在434MHz,功率达到1dBm,相位噪声为-87dBc/Hz@10kHz。此频率源指标满足大多数测量和通信系统要求,可在射频电路中推广使用。
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| 关 键 词： | 频率合成 PLL ADS 低相位噪声 |
Simulation and design of low phase noise frequency synthesizer |
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| Jia Haipeng,Zhang Xiangwen.Simulation and design of low phase noise frequency synthesizer[J].Journal of Guilin Institute of Electronic Technology,2012(4):289-292. |
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| Authors: | Jia Haipeng Zhang Xiangwen |
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| Affiliation: | (School of Computer Science and Engineering,Guilin University of Electric Technology,Guilin 541004,China) |
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| Abstract: | In order to obtain low phase noise and high integration level frequency source,The frequency synthesizer based on PLL was designed.Using RF simulation software ADS,lock time and phase noise were simulated to meet the expected value of the design.Hardware test was done by the VCO PLL chip ADF4360-7,locking frequency is 434 MHz,power is 1 dBm and phase noise is-87 dBc/Hz@10 kHz.It meets requirements of most measurement and communication system.The project can be promoted in RF circuit. |
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| Keywords: | frequency synthesizer PLL ADS low phase noise |
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