基于轮内流水线技术的高性能AES硬件实现设计

为了提升AES的性能,本文采用轮内流水线技术进行AES硬件设计。在对AES轮单元复杂的字节代换/逆字节代换、列变换/逆列变换进行了算法分析的基础上,进行了AES轮单元的轮内7级流水线设计。特别是采用常数矩阵乘积形式和复用列变换进行了逆列变换设计,降低了硬件资源的占用。采用Xilinx ISE10.1工具进行了各个型号FPGA的硬件实现,实验数据表明文中提出的硬件实现方案提升了AES的数据吞吐率与吞吐率/面积比。

The hardware implementation of a high performance AES based on inner pipeline

An inner pipelined hardware design of AES is presented in this paper for the performance improvement of AES. Based on the algorithmic analysis of the SubBytes/invSubBytes and MixColumns/invMixColumns, a 7-stage pipelined structure, which applies the invMixColumns design arithmetic product of constant matrix, is proposed to reduce the to the multiplexing MixColumns and adopts the form of cost of the hardware resources. The implementation of the proposed is carried out in several FPGAs using the Xilinx ISE10.1and the results have shown an improvement in the data throughout ratio and the ratio of data throughout and area.