Characteristics of an address discharge time lag in terms of a wall voltage in an AC PDP

The characteristics of an address discharge have been investigated in terms of a wall voltage, which plays an important role in achieving a high-speed address discharge in an ac plasma display panel. The wall-voltage conditions generated in a reset period are a considerable factor to reduce the address-discharge time lag. Based on the experimental results, the reset driving scheme in which an address bias voltage is applied to the address electrode in a reset period is proposed to enhance the characteristics of an address-discharge time lag.