| 数字锁相环的电源噪声灵敏度分析 |
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| 引用本文： | 王奕婷.数字锁相环的电源噪声灵敏度分析[J].电子科技,2013,26(10):101-104. |
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| 作者姓名： | 王奕婷 |
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| 作者单位： | (西安电子科技大学 电路CAD所,陕西 西安 710071) |
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| 摘 要： | 通过建立电源噪声影响I/O信号抖动的方法学,从而打破狭义电源完整性纯粹追求低噪声的设计思路,佐证了电源噪声灵敏度这一概念。搭建锁相环模型仿真绘制出灵敏度曲线,并通过分析,得到不同频率噪声存在互调的结论,对高速串行链路接口设计具有一定指导性意义。
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| 关 键 词： | 噪声灵敏度 互调 锁相环 电源完整性 |
Sensitivity Analysis of Power Supply Noise of Digital PLL |
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| WANG Yiting.Sensitivity Analysis of Power Supply Noise of Digital PLL[J].Electronic Science and Technology,2013,26(10):101-104. |
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| Authors: | WANG Yiting |
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| Affiliation: | (Institute of Electronic CAD,Xidian University,Xi'an 710071,China) |
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| Abstract: | The methodology of the I/O signal jitter affected by power supply noise is presented,which is a breakthrough to the design idea of pure pursuit of low noise for the special power integrity.The concept of jitter sensitivity is verified.The PLL model is used to draw the curve of sensitivity,which suggests that intermodulation exists among different frequency noises. |
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| Keywords: | sensitivity of noise intermodulation phase locked loop power integrity |
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