多通道升降沿产生激光驱动器超窄脉冲新方法

应用于不同领域的超窄脉冲激光驱动器要求输入脉冲宽度极窄，并且大范围内可调。传统的模拟器件可调性差难以满足要求，数字器件例如专用集成电路(ASIC)尽管脉冲宽度可以实现超窄输出，但是大范围内可调不易满足，并且存在可扩展性差，价格昂贵等特点，同样不利于推广。现场可编程门阵列(FPGA)程控性好，因此在脉冲激光驱动器中的数字脉冲源得到了很好的应用，但是传统的计数方法只能实现脉宽为时钟周期倍数的脉冲输出，因此只能应用于对窄脉宽要求不高的情形。为解决上述问题，本文基于FPGA设计了一种应用于超窄脉冲激光驱动器，在50 MHz时钟频率下利用锁相环倍频成多个通道的基准时钟，并分别利用上升下降沿计数器进行计数，再经不同逻辑运算输出的数字脉冲产生方法。最终的数字电路可以产生脉宽2～50 ns,步长1 ns可调，重复频率1 Hz～1 MHz的数字脉冲信号。最后分析了在高精度锁相环等硬件条件满足的情况下，该方法可以实现亚纳秒脉宽和步长的数字脉冲信号输出，因此具备了很好的可拓展性和前景。

A new method for generating ultra narrow pulse from laser driverswith multi channel rising and falling edges

Ultra narrow pulse laser drivers for various applicationsrequire extremely narrow input pulse widths that are adjustable over a wide range.Traditional analog devices are poorly tunable,which is difficult to meet the requirements.Although digital devices such as Application Specific Integrated Circuit (ASIC) can achieve ultra narrow pulse widths,it is not easily adjustable over a wide range,and has the characteristics of poor scalability and high price,which is also not conducive to promotion.Field Programmable Gate Array (FPGA) has good programmability,so the digital pulse source in the pulse laser driver is well applied.However,the traditional counting method can only realize the pulse output with a pulse width ofa multiple of the clock cycle,so it can only be applied to the situation where the narrow pulse width requirement is not high.In order to solve the above problems,a digital pulse generation method based on FPGA for ultra narrow pulse laser driver is designed,using phase locked loop (PLL) to multiply the reference clock into multiple channels at 50 MHz clock frequency,and using rising and falling edge counters to count respectively,and then outputs through different logic operations.The final digital circuit can generate a digital pulse signal withpulse widths from 2 ns to 50 ns,adjustable steps length of 1ns,and repetition rates from 1 Hz to 1 MHz.Finally,it is analyzed that the method canachieve the digital pulse signal output with sub nanosecond pulse width and step length when the hardware conditions such as high precision phase locked loop are satisfied,so it has satisfying scalability and good prospect.