| 实时图像采集系统的FPGA逻辑设计与实现 |
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| 引用本文： | 戚秀真,周颖.实时图像采集系统的FPGA逻辑设计与实现[J].电子科技,2013,26(4):22-24. |
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| 作者姓名： | 戚秀真 周颖 |
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| 作者单位： | (1.长安大学 信息工程学院,陕西 西安 710064;2.陕西邮电职业技术学院 计算机系,陕西 咸阳 712000) |
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| 摘 要： | 提出了一种实时图像采集系统的设计方案。阐述了图像采集系统中的总线形成、高速缓存和SDRAM控制器3个关键技术,并给出了FPGA控制逻辑和实现方法。该系统时钟＞60 MHz,实现了多分辨率灰度和彩色图像的采集,像素时钟＞30 MHz,帧频没有限制。
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| 关 键 词： | 图像采集 高速缓存 FPGA SDRAM |
Logic Design and Realization of Real-Time Image Acquisition System Based on FPGA |
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| QI Xiuzhen
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ZHOU Ying.Logic Design and Realization of Real-Time Image Acquisition System Based on FPGA[J].Electronic Science and Technology,2013,26(4):22-24. |
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| Authors: | QI Xiuzhen ZHOU Ying |
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| Affiliation: | (1.School of Information Engineering,Chang'an University,Xi'an 710064,China;
2.Department of Computer Science,Shanxi Post and Telecommunication College,Xianyang 712000,China) |
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| Abstract: | A design scheme of real-time image acquisition system is presented in this paper.The key technology of bus generation,high-speed buffer and Synchronous Dynamic Random Access Memory (SDRAM) of the image acquisition system are expatiated.The control logic and realization of FPGA are presented.The AT system clock is more than 60MHz,and the pels clock is more than 30 MHz.The acquisition of grey and color image with high-resolution is realized without limit to the frame rate. |
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| Keywords: | image acquisition high-speed buffer FPGA SDRAM |
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