| 同步时序逻辑电路设计步骤研究 |
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| 引用本文： | 褚德欣,王艳荣. 同步时序逻辑电路设计步骤研究[J]. 电子科技, 2013, 26(4): 169-170,172 |
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| 作者姓名： | 褚德欣 王艳荣 |
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| 作者单位： | (内蒙古工业大学 信息工程学院,内蒙 呼和浩特 010051) |
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| 摘 要： | 通过对时序逻辑电路设计部分教学过程的设计步骤分析研究,强化了原始状态的确定在设计过程中的重要性,在清晰设计思路,强化时序逻辑电路经典的设计方法的同时,补充了与实践应用相关的设计实例,完善了时序逻辑电路的设计步骤。
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| 关 键 词： | 时序逻辑电路 原始状态 电路设计 |
Research on Synchronous Sequential Logic Circuit Design Steps |
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| CHU Dexin , WANG Yanrong. Research on Synchronous Sequential Logic Circuit Design Steps[J]. Electronic Science and Technology, 2013, 26(4): 169-170,172 |
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| Authors: | CHU Dexin WANG Yanrong |
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| Affiliation: | (College of Information Engineer,Inner Mongolia University of Technology,Hohhot 010051,China) |
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| Abstract: | In this paper,the design steps of the sequential logic circuit design part of the teaching process is researched,and the importance of the determination of the original state of the design process is emphasized.Some practical application examples are provided,and the timing logic circuit design steps are optimized. |
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| Keywords: | sequential logic circuit the original state circuit design, |
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