基于FPGA的异步FIFO硬件实现

使用FPGA内部资源BlockRam实现异步FIFO,因为未使用外挂FIFO,使得板卡设计结构简单并减少了硬件板卡的干扰,给硬件调试工作带来了方便,也充分体现了FPGA的优势,这种方法对设计异步FIFO使用具有很好的借鉴意义。实验通过VERILOG编程实现异步FIFO,对程序进行了功能仿真、时序仿真,并下载到FPGA芯片中进行了硬件仿真,实验结果达到了预期的参数要求,完成了FIFO软硬件设计。

Asynchronous FIFO Hardware Design Based on FPGA

Usage of the internal resources of FPGA realizes asynchronism FIFO, because of not using the exterior FIFO, it simplified the design construction, decrease the interference and brought the convenience to adjusting of plank card, and also well incarnate advantage of FPGA. This kind of method has great meaning to the usage of asynchronism FIFO. The experiment realizes asynchronism FIFO with VERILOG program, the result come to an anticipant request of parameter, completing the design of software and hardware in FIFO.