(1) Microelectronics Engineering Group, TEISA Department, ETSIIyT, University of Cantabria, Avda, Los Castros, S/n, 39006 Santander, Cantabria, Spain
Abstract:
The latest versions of the “International Technology Roadmap for Semiconductors” (ITRS) highlight that verification has changed
from playing a relatively minor supporting role in the design process to becoming the dominant cost. This situation is the
result of the exponential growth of the functional complexity of designs and the historical emphasis of CAD tools in other
areas of the design process such as automatic synthesis or place-and-route. The problem is even worst in embedded systems
that normally integrate functionally complex hardware and software parts. This work presents a new verification technique
based on interval analysis that can handle embedded designs described at behavioural level. The proposed technique is able
to verify assertions that the users insert in software and hardware tasks. It shows very promising results in systems that
cannot be efficiently verified with other tools (e.g. data-dominated designs).