并行化改进遗传算法的FPGA高速实现方法

为提高硬件运行速度和资源利用率,利用硬件并行化的思想改进传统算法的处理模式,将遗传算法传统实现方法的控制部分分解到各模块内部,按照流水线模式,应用现场可编程逻辑门阵列(FPGA)高速实现。综合后时钟频率达到137.08 MHz,演化1代需64个时钟周期,即0.467μs。实现结构节约硬件资源,效率高,使大规模遗传算法的高速硬件实现成为可能。

Methodology of realizing FPGA for improved parallel genetic algorithm

To enhance the operation speed and utilize the resource,according to the idea of hardware parallel method,one traditional implementation of genetic algorithms is improved by separating controlling part into other components and using Field Programmable Gate Array(FPGA) to realize control in pipelining mode.The result of synthesis shows its frequency can reach 137.08 MHz for evolution of a generation needing 64 cycles(namely 0.467 μs).With optimized hardware resources and high efficiency,the realized structure demonstrates the possibility of large-scale and high-speed hardware realization of genetic algorithms.