| 一种低功耗高精度Sigma-Delta调制器 |
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| 引用本文： | 詹陈长,周晓方,周电. 一种低功耗高精度Sigma-Delta调制器[J]. 固体电子学研究与进展, 2007, 27(3): 375-379 |
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| 作者姓名： | 詹陈长 周晓方 周电 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海,201203 |
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| 基金项目： | 国家高技术研究发展计划(863计划) |
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| 摘 要： | 提出了一种改进的三阶单环Sigma-Delta调制器,噪声传递函数采用前馈方式实现极点,降低了积分器输出信号的幅度,从而降低功耗;采用局部反馈实现零点,从而优化了输出信噪比。采用0.35μm CMOS工艺设计了该调制器,过采样率128,信号带宽24kHz,分辨率16bit,在3.3V工作电压下,模拟电路部分功耗2.7mW,数字部分功耗0.5mW。电路用开关电容技术实现,在HSPICE中通过多工艺角验证。
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| 关 键 词： | 低功耗 高精度 Sigma-Delta调制器 互补金属氧化物半导体 |
| 文章编号： | 1000-3819（2007）03-375-05 |
| 修稿时间： | 2006-10-25 |
A Low-power High-resolution Sigma-Delta Modulator |
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| ZHAN Chenchang,ZHOU Xiaofang,ZHOU Dian. A Low-power High-resolution Sigma-Delta Modulator[J]. Research & Progress of Solid State Electronics, 2007, 27(3): 375-379 |
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| Authors: | ZHAN Chenchang ZHOU Xiaofang ZHOU Dian |
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| Abstract: | A modified third order single loop sigma-delta modulator is proposed in this paper. The poles of the noise transfer function(NTF) are realized by feed forwards, reducing the output amplitude of integrators, thus lowering down power consumption. Local feedback is used to add zeros to the NTF thus enhancing the signal-to-noise ratio. The modulator is designed using 0.35 μm CMOS process. The over sampling ratio is 128, with a signal bandwidth of about 24 kHz. The effective number of bits is 16. When the power supply is 3.3 V, the power consumption of analog part is 2.7 mW and that of digital part is 0.5 mW. The modulator is implemented with switched-capacitor techniques. Multiple process corners simulation in HSPICE is carried out to verify the design. |
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| Keywords: | low-power high-resolution Sigma-Delta modulator CMOS |
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