低漏电流、抑制NBTI效应的多米诺电路

NBTI导致的晶体管老化成为影响电路稳定性的主导因素，同时，降低电路的泄漏功耗是电路设计的目标之一。多米诺电路广泛应用在高性能集成电路中。本文提出了一种多米诺电路用来抑制NBTI引起的多米诺电路衰退并同时降低待机模式下的泄漏电流。在待机模式下，利用2个晶体管将标准多米诺电路的动态节点和输出节点同时上拉为电源电平，从而将保持器和输出反相器中的pMOS晶体管同时置为NBTI的恢复模式。使用全0输入向量和其中增加的一个晶体管的堆栈效应降低待机模式下多米诺电路的泄漏电流。实验表明针对NBTI效应，该方法降低了最多33%的性能衰退，并同时减少了最多79%的泄漏电流。

Low-Leakage and NBTI-Mitigated N-Type Domino Logic

NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are extensively applied in high-performance integrated circuits. A circuit technique to mitigate NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to standard domino circuit to pull both dynamic node and output up to VDD, which put both keeper and inverter pMOS transistor into recovery mode in standby mode. Due to stack effect, leakage current is reduced by all-0 input vector and the added transistor. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.