| 一种高效的可编程时钟源设计 |
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| 引用本文： | 韦建荣,林君,柏荷. 一种高效的可编程时钟源设计[J]. 电测与仪表, 2007, 44(3): 55-58 |
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| 作者姓名： | 韦建荣 林君 柏荷 |
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| 作者单位： | 吉林大学,仪器科学与电气工程学院,长春,130026 |
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| 摘 要： | 介绍了一种采用可编程器件实现的时钟源.通过控制一个N位累加器累加,取其最高位,即可得到可编程时钟源.详细介绍了累加器的流水线实现过程,大大提高了器件允许的最高工作频率.实验结果验证了该时钟源具有精度高、稳定性好等优点.
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| 关 键 词： | 可编程时钟源 累加器 流水线 CPLD FPGA |
| 文章编号： | 1001-1390(2007)03-0055-04 |
| 修稿时间： | 2006-10-23 |
Design of a high efficient programmable clock |
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| WEI Jian-rong,LIN Jun,BAI He. Design of a high efficient programmable clock[J]. Electrical Measurement & Instrumentation, 2007, 44(3): 55-58 |
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| Authors: | WEI Jian-rong LIN Jun BAI He |
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| Abstract: | This paper introduces a clock designed in programmable device.Through an N-bit accumulator and then get its highest bit to generate the programmabl controlling e clock. It introduces the pipelining design method for accumulator in detail, which greatly improved the highest operating frequency that the device allows. The experimental result certifies that this programmable clock has many advantages, such as high precision, good stability. |
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| Keywords: | programmable clock accumulator pipeline CPLD FPGA |
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