Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end |
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Authors: | Chung-Yu Wu Wen-Chieh Wang Fadi R. Shahroury Zue-Der Huang Hao-Jie Zhan |
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Affiliation: | (1) Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering, National Chiao Tung University, Hsinchu, 300, Taiwan |
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Abstract: | A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P-1 dB)(P_{{-1},{rm dB}}) of −13.5 dBm and the input-referred third-order intercept point (P IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 ×0.721.45 times 0.72 mm2 including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies. |
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