| 数字下变频及抽取的FPGA实现 |
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| 引用本文： | 侯永宏,侯春萍,曹达仲,戴居丰. 数字下变频及抽取的FPGA实现[J]. 电路与系统学报, 2005, 10(1): 123-126 |
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| 作者姓名： | 侯永宏 侯春萍 曹达仲 戴居丰 |
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| 作者单位： | 天津大学,电子信息工程学院,天津,300072 |
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| 摘 要： | 在FPGA上实现了对高频窄带数字信号的下变频和取样率转换,由于完全避免了需要大量逻辑资源的乘法器和数字振荡器,其结构大为简化,再加上采用了流水处理结构,使其处理速度超过100M样点每秒,此外它还具有结构简单,重配置能力强的优点,具有广阔的应用前景.
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| 关 键 词： | 积分梳状滤波器 抽取 现场可编程门阵列(FPGA) |
| 文章编号： | 1007-0249(2005)01-0123-04 |
| 修稿时间： | 2003-12-08 |
FPGA implementation of digital down conversion and decimation |
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| HOU Yong-hong,HOU Chun-ping,CAO Da-zhong,DAI Ju-feng. FPGA implementation of digital down conversion and decimation[J]. Journal of Circuits and Systems, 2005, 10(1): 123-126 |
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| Authors: | HOU Yong-hong HOU Chun-ping CAO Da-zhong DAI Ju-feng |
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| Abstract: | Digital down conversion and decimation were implemented in FPGA. Due to completely eliminate Multiplier and digital oscillator which will consume a huge amount of FPGA resources, its complexity is reduced significantly. Combined with pipeline structure in comb stage, its process speed exceeds 100M samples per second. The design has strong reconfigurability and exhibits strong application prospect. |
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| Keywords: | cascaded integrator-comb (CIC) decimation FPGA |
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