集成电路局部缺陷模型及其相关的功能成品率分析

大规模集成电路（VLSI）使亚微米特征尺寸的大面积集成电路制造以及集成数百万个器件在一芯片上成为可能。然而，缺陷的存在致使电路版图的拓扑结构发生变化，产生IC电路连接错误，导致电路丧失功能，从而影响IC的成品率，特别是功能成品率。文章主要对缺陷的轮廓模型、空间分布模型和粒径分布模型作了介绍；对集成电路成品率的损失机理作了详细论述。最后，详细介绍了功能成品率的分析模型。

A Local Defect Model of IC's and Analysis of Its Related Functional Yield

Current very-large-scale-integration (VLSI) technology makes it possible to manufacture large-area integrated circuits with sub-micrometer feature sizes and integrate millions of elements into a single chip. However, imperfections in the fabrication process result in yield reduction, especially for IC functional yield. Models of the defect outline, the spatial distribution and the size distribution statistics are described in the paper. Mechanisms of the IC functional yield loss are discussed in particular and the analysis model of the IC functional yield is introduced in detail.