| JTAG软核设计与仿真 |
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| 引用本文： | 吕彩霞,李哲英. JTAG软核设计与仿真[J]. 数字社区&智能家居, 2006, 0(23) |
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| 作者姓名： | 吕彩霞 李哲英 |
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| 作者单位： | 北京交通大学电子信息工程学院电子工程系 北京100044(吕彩霞)，北京联合大学信息学院 北京100101(李哲英) |
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| 摘 要： | JTAG边界扫描测试是一种新型的VLSI电路测试及可测试性设计方法。本文论述了边界扫描技术的结构特征及软核设计方法,并分析了JTAG电路中数据传输的路径及电路对速度的影响,以采样指令为例进行了功能仿真。
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| 关 键 词： | JTAG 边界扫描 逻辑仿真 |
JTAG Soft Core Define and Emulation |
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| LV Cai-xia,LI Zhe-ying. JTAG Soft Core Define and Emulation[J]. Digital Community & Smart Home, 2006, 0(23) |
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| Authors: | LV Cai-xia LI Zhe-ying |
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| Affiliation: | LV Cai-xia1,LI Zhe-ying2 |
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| Abstract: | Boundary-scan technology is a new and effective way of test and design-for-testability for VLSI circuits. In the paper the boundary-scan the configuration character and soft core design methods are introduced. This paper also analyze the route of data transfers and effect on speed in JTAG circuit. taking sampling instruction for example, function of soft core is emulated. |
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| Keywords: | JTAG boundary-scan soft core |
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