Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability

Technology scalings in semiconductors have enabled the integration of dozens of processing elements (PEs) onto a single chip (MPSoC). Scheduling application tasks onto the target MPSoC has been widely reported in the literature. Both technology scalings and resource competitions among applications have led to the variations of availability resources at runtime. While adaptive static schedules with predictable responses to runtime resource variations have consequently been proposed, a large number of task migrations upon PE failures in this reconfigurable schedule scheme will lead to excessive migration cost among processors and performance degradation. In this paper, we present an algorithm to reduce the number of task migrations while retaining the benefits of the fore techniques. Through embedding several soft constraints into the baseline heuristic scheduling algorithm, the proposed algorithm can decrease the number of task migrations significantly on the basis of holding the advantages of the initial dynamic reconfigurable schedule scheme. The performance evaluation of the proposed technique is carried out by incorporation into a well known heuristic scheduling algorithm. The simulation results confirm its effectiveness in minimizing the number of task migrations during dynamic reconfiguration.