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| 基于FPGA的数字锁相环实现与性能分析 | |
| 引用本文： | 刘秋明,蔡志勇,王健.基于FPGA的数字锁相环实现与性能分析[J].电子质量,2009(7):15-16,23. |
| 作者姓名： | 刘秋明 蔡志勇 王健 |
| 作者单位： | 1. 南昌在学,江西,南昌,330031 2. 南昌在学,江西,南昌,330031;洪都集团飞机设计所,江西,南昌,330024 3. 深圳信桥科技有限公司,广东,深圳,518057 |
| 摘 要： | 在数字通信系统中,对传输数据的位同步信号提取非常重要.在基于FPGA的数字系统中,通常是设计一个数字锁相环(DPLL)来解决这些问题.文章设计一种新的利用bang-bang鉴相器实现的DPLL,bang-bang鉴相器能直接从接收数据流中提取位时钟信号,且在减少抖动、侪频、时钟恢复和数据同步有很好的优越性.分析了,整个数字锁相环在无高斯白噪声环境下的性能,最后给出了整个锁相环的波形仿真. |
| 关 键 词： | bang-bang鉴相器 波形仿真 环路基本方程 性能分析 |
The Implementation and Analysis of Digital Phase-locked Loop Based on FPGA |
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| Liu Qiu-ming,Cai Zhi-yong,Wang Jian.The Implementation and Analysis of Digital Phase-locked Loop Based on FPGA[J].Electronics Quality,2009(7):15-16,23. | |
| Authors: | Liu Qiu-ming Cai Zhi-yong Wang Jian |
| Affiliation: | Liu Qiu-ming1,Cai Zhi-yong1,2,Wang Jian3(1. Nanchang University,Jiangxi Nanchang 330031,2. Hongdu Aircraft Research Institute,Jiangxi Nanchang 330024,3. Pacbridge Technology Company,Guangdong Shenzhen 518057) |
| Abstract: | In the digital communication system,It's very important to refine bit synchronized signal. Based on the FPGA communication system,we usually design a digtal phase-locked loop(DPLL) to solve the problem. This papper use a new kind of bang-bang phase-detector to implement the DPLL,which can refine bit clock signal directly from the receive data stream,and it works well in jitter reduction,clock multiplication,clock and data recovery. Also analysis the DPLL' performance without Gaussian white noise enviroment.... |
| Keywords: | bang-bang detector wave simulation loop formula performance's analysis |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |