A Resource-Efficient Communication Architecture for Chip Multiprocessors on FPGAs |
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Authors: | Xiaofang??Wang Swetha?Thota |
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Affiliation: | Xiaofang(Maggie)Wang,Swetha Thota |
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Abstract: | Significant advances in field-programmable gate arrays (FPGAs) have made it viable to explore innovative multiprocessor solutions
on a single FPGA chip. For multiprocessors, an efficient communication network that matches the needs of the target application
is always critical to the overall performance. Wormhole packet-switching network-on-chip (NoC) solutions are replacing conventional
shared buses to deal with scalability and complexity challenges coming along with the increasing number of processing elements
(PEs). However, the quest for high performance networks has led to very complex and resource-expensive NoC designs, leaving
little room for the real computing force, i.e., PEs. Moreover, many techniques offer very small performance gains or none
at all when network traffic is light while increasing the resource usage of routers. We argue that computation is still the
primary task of multiprocessors and sufficient resources should be reserved for PEs. This paper presents our novel design
and implementation of a resource-efficient communication network for multiprocessors on FPGAs. We reduce not only the required
number of routers for a given number of PEs by introducing a new PE-router topology, but also the resource requirement of
each router. Our communication network relies on the NEWS channels to transfer packets in a pipelined fashion following the
path determined by the routing network. The implementation results on various Xilinx FPGAs show good performance in the typical
range of network load for multiprocessor applications. |
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