Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs than in 2D ICs. Since the through-the-silicon via is large and can only be inserted into whitespace of the device layer, planning STS-via for thermal optimization may affect the interconnection wire length. Therefore, in order to make STS-via planning more flexible, we integrated STS-via with pin assignment. In this paper, we use min-cost maximum flow algorithm for STS-via planning and pin assignment simultaneously. Experimental results show that our approach can reduce both temperature and wire length effectively with short runtime.