Wave-pipelined intra-chip signaling for on-FPGA communications |
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Authors: | Terrence Mak [Author Vitae] Pete Sedcole [Author Vitae] |
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Affiliation: | a Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Road, London, UK b Department of Computing, Imperial College London, Exhibition Road, London, UK |
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Abstract: | On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge. |
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Keywords: | FPGAs On-chip communication Wave-pipelining Interconnect model Throughput Source synchronous |
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