A digitally controlled PLL for SoC applications |
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Authors: | Olsson T Nilsson P |
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Affiliation: | Lund Univ., Sweden; |
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Abstract: | A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-/spl mu/m standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested. |
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