New method for threshold voltage extraction of high-voltage MOSFETs based on gate-to-drain capacitance measurement

This letter reports on the extraction of the threshold voltage of laterally diffused MOS transistors. A clear analysis of the device physics is performed, highlighting the correlation between the change of the electron charge distribution along the channel and the device capacitance variations when the gate voltage is swept. Using numerical simulations, it is shown that the peak of the gate-to-drain capacitance is related to the transition of the surface from weak to moderate inversion in the intrinsic MOS transistor at the location of the maximum doping concentration, which corresponds to the threshold voltage of the device according to the MOS theory. Comparison between conventional I/sub D///spl radic/g/sub m/ extraction and the new proposed capacitance peak method is performed on both technology computer-aided design simulations and measurements in order to confirm the new experimental technique and related theory.