用面对面叠加法实现芯片的3D集成

面对面芯片叠加使一颗芯片置于另一颗芯片的倒装凸块阵列中,从而极大减小了封装厚度。POSSUMTM封装是指两颗或多颗芯片用面对面的方式叠加,其中较小的芯片置于较大芯片上没有互联倒装凸块的区域。较小的芯片在薄化后通过铜柱微块组装到较大的芯片上。因此,薄化了的较小芯片和它的铜柱微块的总体高度就比其附着的较大芯片的倒装凸块经回流后的高度要低很多。一旦组装完毕,较小芯片就被有效地夹在上面的较大芯片和下面的基板中,同时被一环或多环倒装锡凸块包围。底部填充剂的使用同时保证了铜柱和无铅锡凸块在测试和使用中的可靠性要求。因为信号在两颗芯片的表面运行,所以互连线极短,可以实现近距离信号匹配,和小电感的信号传输。这种面对面芯片叠加方式保证了很好的芯片间信号传输的完整性,是穿硅孔(TSV)封装技术的低成本的有效替代。

Realizing 3D IC Integration with Face-to-Face Stacking

Face to face die slackin one die can be ＂hidden＂ within the g can offer bump arra more devices assembled face-to-face where a clever approaches to minimize overall stacked height, especially when y of another. The POSSUMTM stacked die configuration describes two or smaller die is nested within the I/O-free areas of the larger die. The smaller die is thinned significantly and joined to the larger die through copper pillar micro-bumps. The combined height of the thinned die and its copper pillar bumps are much less than the collapsed flip chip bumps that mount the larger die to the substrate or PCB. Once mounted, the smaller die is effectively sandwiched between the larger top die, the bottom substrate, and surrounded by one or more rings of solder bumps. Underfill ensures that both the copper pillar and lead free solder bumps meet package and board level reliability requirements. Because the signals are rout- ed between the top sides of the two devices, the I/Os can be closely matched up, ensuring extremely short interconnect lengths and very low inductance copper pillar joints. The resulting structure ensures high die-to-die signal integrity anti provides a cost effective alternative to a through silicon via （ TSV ） solution.