高效精确的创新AOCV芯片设计流程

由于工艺的偏差主导了大部分器件的长度和宽度,所以这种偏差在更先进的工艺节点上尤其重要。传统的片上偏差(on-chip variation,OCV)已经使用了一个下降因子(derating factor)在所有的时序路径上,去模仿工艺变化,这样对于增加工艺偏差来说太悲观了。对比与传统的片上偏差,先进的片上偏差(Advanced OCV,AOCV)在不同的时序路径上给出了不同的下降因子。这样就可以减轻由于下降和减少过度设计和时序收敛周期而引起的过度悲观。这篇文章中我们介绍了一种创新的AOCV芯片设计流程,包括AOCV表格生成,执行和si gn-of f阶段。在AOCV表格生成中,我们重点介绍如何选择设计相关的工艺偏差参数。执行相关的AOCV表格可以加快转换周期,而且EDA时序修改工具能支持AOCV表格。在sign-of f阶段,我们对比了Synopsys Primetime基于路径分析AOCV的实验结果,表明误差在1%以内。

Innovative AOCV Chip Design flow with Efficiency and Accuracy

Process variation becomes particularly important in advance process nodes as the variation leads to a larger percentage of the full length or width of the device. Traditional on-chip-variation has been single derating factor on all timing paths to model process variation; it is too pessimistic for introduced by adding the increasing process variaCompared with traditional way, it can drastically alleviate paper, we introduce an AOCV OCV, advanced-OCV gives different derating values on different timing paths. In this over-pessimism of derating and reduce over-design and timing closure cycles. In this flow which includes AOCV table generation, implementation and sign-off. In AOCV table generation, we focus on how to select design-oriented process variation parameters. Implementation-oriented AOCV table can lead to faster turnaround time, and EDA timing fixing tools can support the AOCV table. In sign-off stage, we compared results of Synopsys Primetime AOCV-PBA against those of Synopsys HSPICE, and the experiment results show that the mismatches are less than 1%.