用2.5D TSV实现多处理器SiP功能

本项目由Open-Silicon,GLOBALFOUNDRI ES和Amkor三家公司合作完成。两颗28nm的ARM处理器芯片,通过2.5D硅转接板实现集成。芯片的高性能集成通常由晶体管制程提高来实现,应用2.5D技术的Si P正成为传统芯片系统集成的有效替代。Open-Silicon负责芯片和硅转接板的设计,重点在于性能优化和成本降低。GLOBALFOUNDRI ES采用28nm超低能耗芯片工艺制造处理器芯片,而用65nm技术制造2.5D硅转接板。包括功耗优化和功能界面有效管理等概念得到验证。硅基板的高密度布线提供大量平行I/O,以实现高性能存储,并保持较低功耗。所开发的EDA设计参考流程可以用于优化2.5D设计。本文展示了如何将大颗芯片重新设计成较小的几颗芯片,通过2.5D硅转接板实现Si P系统集成,以降低成本,提高良率,增加设计灵活性和重复使用性,并减少开发风险。

Enabling a multiple processor SiP with 2.5D TSVs

A collaborative program between Open-Silicon, functional SiP solution featuring two 28nm logic chips with GLOBALFOUNDRIES and Amkor Technology produced a embedded ARM processors that were interconnected using 2.5D through silicon via （ TSV ） interposer technology. The adoption of 2.5D technology is increasingly being viewed as an alternative to traditional scaling at the transistor level. The design featured two ARM Cortex-A9 processors manufactured with GLOBALFOUNDRIES＇ 28nm-SLP （ Super Low Power ） process technology. The processors were assembled onto a 65nm silicon interposer with TSVs to facilitate high bandwidth communication between the chips. Open-Silicon designed the logic die to demonstrate several downstream efficiencies for cost savings and fast time-to-market. The 2.5D approach allowed device and system designers to decouple functions from a single SoC solution and provided a pivotal demonstration of heterogeneous die integration. The emphasis on concurrent processor and interposer design optimized performance and design-for-cost advantages. Several concepts were demonstrated including power optimization and the effective management of interfaces between the various functions. Along with the processors, the system featured DDR3, USB and AXI bridge interfaces. High performance memory that uses massively parallel I/Os keeps power down and is facilitated by the dense routing enabled by silicon interposers. One deliverable from the program was a special EDA reference flow to address the requirements of the 2.5D design including top-level I/O placement and routing, multi-layer TSV and interconnect layout, front-side and back-side copper pillar and flip chip bumps, and redistribution layers. Chip design and silicon process node can either preserve or limit inter-chip communication when comparing SoC versus multichip or system -in-package （ SiP ） approaches. Connecting two dual-core processors within a single package illustrated the expansion of function through multiple die without reduction