对数跳跃加法器的静态CMOS实现

介绍了一种32位对数跳跃加法器结构.该结构采用ELM超前进位加法器代替进位跳跃结构中的组内串行加法器,同ELM相比节约了30%的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用Ling算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现"与-民或"功能;1.0μm CMOS工世实现的32位对数跳跃加法器面积为0.62mm2,采用1μm和0.25μm 工世参数的关键路径延迟分别为6ns和0.8ns,在100MHz下功耗分别为23和5.2mW.

Static CMOS Implementation of Logarithmic Skip Adder

Circuit design of 32-bit logarithmic skip adder (LSA) is introduced to implement high performance,low power addition.ELM carry lookahead adder is included into groups of carry skip adder and the hybrid structure costs 30% less hardware than ELM.At circuit level,a carry-incorporating structure to include the primary carry input in carry chain and an "and-xor" structure to implement final sum logic in 32-bit LSA are designed for better optimization.For 5V,1μm process,32-bit LSA has a critical delay of 5.9ns and costs an area of 0.62mm2,power consumption of 23mW at 100MHz.For 2.5V,0.25μm process,critical delay of 0.8ns,power dissipation of 5.2mW at 100MHz is simulated.