适用于ASIC的高速低功耗逻辑单元

本文介绍一种ECL电路结构形式的ASIC逻辑单元的设计和应用。该单元使用2.5V的电源,内部开关电流设计为0.5mA,逻辑摆幅设计为340mV,输入输出均采用双向互补信号。它具有信息的基本记忆功能,用它进行多级组合配套设计,可制作不同模数的分频器、寄存器和计数器等。设计灵活,功能强,电路速度快,功耗低,仅为具有相同功能的普通ECL电路的1/30。这些电路可用在通讯机、电子控制系统、电子测量系结中作高速数字锁相环,数字信号处理的专用集成电路。

A High Speed, Low Power Logical Block for the Implementation of Application-Specific Integrated Circuits

This paper describes the design of an ECL logical block and its applications to the implementation of application-specific integrated circuits. In the design, the power supply, the internal switching current and the logic swing are set to be 2.5V, 0.5mA and 340mV repectively and bidirectional complementary signals are used for both the input and output. With multilevel combination, the logical block can be used to implement frequency dividers, registers and counters of diffeient modulus.