0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficientredundancy and enhanced testability |
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| Authors: | Kikukawa H Tomishima S Tsuji T Kawasaki T Sakamoto S Ishikawa M Abe W Tanizaki H Kato H Uchikoba T Inokuchi T Senoh M Fukushima Y Nirro M Maruta M Shibayama A Ooishi T Takahashi K Hidaka H |
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| Affiliation: | Adv. LSI Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd, Kyoto; |
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| Abstract: | This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm 2 and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm2 and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment |
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