嵌入式处理器中写缓冲电路的设计

为了减少CPU对主存进行写操作时的等待时间,提高嵌入式系统的整体效率,设计了一款含有8个数据缓冲槽和4个地址缓冲槽的写缓冲。该写缓冲采用特殊的移位控制电路和附加的标志位,实现数据、地址的自动移位和映射功能。利用HSIM仿真工具对电路进行了仿真和验证,结果表明,该写缓冲能正确快速地实现数据与地址的先进先出(FIFO)功能,有效地减少了CPU的等待时间,提高了系统的整体效率。

Design of Write Buffer for Embedded Processor

In order to reduce the waiting time of write operations from CPU to main memory and improve the whole efficiency of embedded system,a kind of write buffer including 8 data buffer slots and 4 address buffer slots is designed.A special shift control circuit and one additional flag bit are provided to realize the functions of auto shift and mapping of data and addresses.Hsim simulation tool is used to simulate and verify the circuits.The result shows this write buffer can realize the First-In-First-Out(FIFO) function of data and addresses correctly and fast,reduce the CPU waiting time efficiently,and thus improve the whole efficiency of system.