| 用于大规模集成电路的多级布局规划设计 |
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| 引用本文： | 徐正,吉村猛. 用于大规模集成电路的多级布局规划设计[J]. 电子测量技术, 2009, 32(5): 47-49 |
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| 作者姓名： | 徐正 吉村猛 |
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| 作者单位： | 上海大学通信与信息工程学院,上海,200072;日本早稻田大学情报生产系统研究科,北九州市;日本早稻田大学情报生产系统研究科,北九州市 |
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| 摘 要： | 本文提出了一种适用于处理大规模集成电路设计的布图规划问题的V型多级不可分割固定边框布图规划算法。该算法以追求电路设计在短耗时前提下的最短布线为目的,同时满足电路原本的面积边框限制。通过计算机仿真,实验结果体现了所提出多级布局规划算法的有效性。
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| 关 键 词： | V型多级构架 固定边框布图规划 大规模集成电路设计 |
Multilevel floorplanning sesign for large-scale integrated circuits |
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| Xu Zheng,Yoshimura Takeshi. Multilevel floorplanning sesign for large-scale integrated circuits[J]. Electronic Measurement Technology, 2009, 32(5): 47-49 |
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| Authors: | Xu Zheng Yoshimura Takeshi |
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| Affiliation: | 1.School of Communication and Information Engineering;Shanghai University;Shanghai 200072;2.Graduate School of Information;Production and Systems;Waseda University;Kitakyusyu Japan |
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| Abstract: | In this paper,we propose a multilevel fixed-outline floorplanning method to deal with floorplanning problem for the large-scale integrated circuit designs.We engage in getting a better result with minimized wirelength,and at the same time,the result must match the fixed-outline restraint.We prove the feasibility by computer,and the experimental results show the effectiveness and efficiency of the algorithm. |
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| Keywords: | V-shaped multilevel framework fixed-outline floorplanning LSI design |
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