Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography |
| |
| Authors: | Wong WS Ready SE Jeng-Ping Lu Street RA |
| |
| Affiliation: | Palo Alto Res. Center, CA, USA; |
| |
| Abstract: | A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 /spl times/ 64 pixel (300 /spl mu/m pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm/sup 2//V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/. |
| |
| Keywords: | |
|
|
