| DTW的ASIC实现算法研究 |
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| 引用本文： | 李韬,贺前华,王前.DTW的ASIC实现算法研究[J].微电子学,2004,34(3):281-284. |
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| 作者姓名： | 李韬 贺前华 王前 |
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| 作者单位： | 华南理工大学,电子与信息学院,广东,广州,510640 |
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| 基金项目： | 国家自然科学基金(60172064,69881001)，广东省攻关项目(粤财企[2003]259号) |
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| 摘 要： | 通过分析DTW算法，提出了一种适合ASIC实现的心动阵列结构。仿真结果表明，该并行VLSI处理器阵列系统能够在N M-1个时钟周期内计算出两个模板的匹配加权距离。较之基于通用处理器串行实现的DTW算法需要的3pMN／2个时钟周期，该算法节省了大量的运算时间。
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| 关 键 词： | DTW 语音识别 心动阵列 专用集成电路 |
| 文章编号： | 1004-3365(2004)03-0281-04 |
A Study on Dynamic Time Warping Algorithm and Its ASIC Implementation |
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| LI Tao,HE Qian-hua,WANG Qian.A Study on Dynamic Time Warping Algorithm and Its ASIC Implementation[J].Microelectronics,2004,34(3):281-284. |
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| Authors: | LI Tao HE Qian-hua WANG Qian |
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| Abstract: | By analyzing the Dynamic Time Warping (DTW) algorithm, a systolic array architecture for computations in DTW is described. Results from simulation show that the parallel processor array can finish calculation in M+N-1 clock cycles. The new algorithm requires less operation time than the serial algorithm based on general processors, which need 3pMN/2 clock cycles. The parallel algorithm can be implemented in ASIC. |
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| Keywords: | DTW Speech recognition Systolic array ASIC |
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