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| 高速率低功耗FIR数字滤波器实现 | |
| 引用本文： | 徐红,叶丰,黄朝耿. 高速率低功耗FIR数字滤波器实现[J]. 电视技术, 2014, 38(23) |
| 作者姓名： | 徐红 叶丰 黄朝耿 |
| 作者单位： | 1. 浙江工业大学信息工程学院,浙江杭州,310023 2. 杭州国芯科技股份有限公司,浙江杭州,310012 3. 浙江财经大学信息学院,浙江杭州,310018 |
| 基金项目： | 浙江省自然科学基金项目 |
| 摘 要： | 利用硬件描述语言在ASIC上对FIR数字滤波器进行了设计和综合。利用子项空间技术有效地减少了多常系数乘法中加法器的个数,并通过限制加法器深度来进一步降低高速率约束条件下的实现难度。综合结果表明,该方法可以有效降低硬件的实现面积,适用于高吞吐率低功耗的数字系统设计。 |
| 关 键 词： | FIR数字滤波器 多常数乘法 子项空间技术 加法器深度 ASIC |
| 收稿时间： | 2014-05-12 |
| 修稿时间： | 2014-06-18 |
Implementation of Highspeed and Low Power Consumption FIR Digital Filters |
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| Xu Hong,Ye Feng and Huang Chaogeng. Implementation of Highspeed and Low Power Consumption FIR Digital Filters[J]. Ideo Engineering, 2014, 38(23) | |
| Authors: | Xu Hong Ye Feng Huang Chaogeng |
| Affiliation: | College of Information Engineering, Zhejiang University of Technology,Hangzhou Nationalchip Science&Technology Co. Ltd.,School of Information, Zhejiang University of Finance & Economics |
| Abstract: | In this paper, a hardware technique for implementing FIR filters on ASIC is proposed. The coefficient multipliers are realized with shifters and adders, and the subexpression space technology is adopted, which can effectively reduce the number of adders in the filter. In order to reduce the complexity of implementation, the adder depth is limited under the high rate constraints. The results of hardware synthesis show that the proposed method can efficiently save area consumption, which can be used to design the high throughput digital systems. |
| Keywords: | FIR digital filter design multiple constants multiplication subexpression space technology adder depth ASIC |
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