片上网络中降低信号串扰的方法

NOC（片上网络）的体系结构解决了SOC（片上系统）在大规模集成IP核时面临的一些难题，但其串扰问题对电路性能的影响也越来越明显。基于DSM（深亚微米）下的总线模型，分析了信号串扰引起的总线延时问题，同时比较了3种减小总线串扰的编码方案。并采用0．13μmCMOS工艺对性能较优的DAP编码方案进行了电路仿真，得到了不同长度和宽度下的总线延时。结果表明，采用减少信号串扰的编码方法可以有效地降低总线的串扰，减少信号延时，这一效果当总线较宽或走线较长时尤其明显，同时也证明了0．13μmCMOS工艺下电路仿真结果与理论计算结果的一致性。

Method of Crosstalk Reduction in the Network on Chip

Network-on-chip （NOC） configuration has solved some problems appeared in the large-scale integrated IP cores in SOC. But the crosstalk problem on NOC bus has become more and more significant. In this paper, we analyse the single delay due to the capacitive crosstalk of the deep submicron （DSM） based bus model, and we compare three crosstalk reduction codes. In the simulation, we choose 0.13 μm CMOS technology, perform some circuit simulations with the more superior DAP code and compare the results of different bus length and different bus width. We show that coding method is a better alternative for delay reduction, and verify that the simulation results using the 0.13 μm CMOS technology are identical with the theoretical calculation results.